99国产精品一区二区|亚洲国产一区二区三区日本久久久|国产女同无遮挡|精品综合在线,亚洲最大成人网色,日本xxx大片免费观看,国产成人一区二区三区精

崗位職責(zé):

1. Develop advanced standard cell and GPIO libraries on advanced process technologies (6nm, 7nm, 12/16nm, 22/28nm, etc.)
2. Take challenging tasks from circuit design to SOC design to achieve world-class PPA performance (high-performance, low-power, and area-effective)

1. Good knowledge of circuits design. Experience in digital circuit or analog design is preferred.
2. Experience in Cadence/Synopsys/Mentor EDA tools and Linux/Unix environment is preferred.
3. CAD and script capability such as Python/Perl/Shell is preferred.
4. Solid understanding of device scaling challenges and circuit-process technology interactions applicable for advanced FinFET nodes is a plus.
5. Experience in reliability (EM, high-temperature aging effects, etc.) is a plus
6. Self-motivated and hard work.